1. Field of the Invention
The invention relates to the field of phase locking circuits, and in particular to delay locked loops.
2. Description of Related Art
The synchronization of multiple clocked circuits operating in a system is a problem faced by many system designers. Synchronizing the operation of multiple circuits within a system minimizes timing errors.
In high-speed systems, the phase alignment of the clock signal at the input of each clocked circuit must be maintained with high precision. Clock signals can easily lose phase alignment when passing through intermediate circuits with variable propogation delays. Variations in propagation delay between circuits is caused by differences in circuit structure and variables in the manufacturing process. Manufacturing variables affect parameters such as gains, threshold voltages, impedances, and capacitances. The variations are often small, but even small variations can cause clock phase alignment errors when the clock frequency is on the order of 33 MHz to 66 MHz or higher.
The effect of these variations can be reduced by measuring the propagation delays of individual circuits and matching them with circuits with similar propagation delays. Such matching is, at best, inconvenient in the manufacturing and maintenance of the computer systems.
In a high-speed, multiple chip synchronous computer, the phase difference between clock signals in different parts of the system typically must be held to 100 picoseconds or less. One cause of phase differences in clock signals are propogation delays in clock buffers. Clock buffers are used throughout the system to regenerate the reference clock to drive local circuits, boosting the clock current to provide the proper fan-out. Clock buffers typically create a delay of 5 nanoseconds for 66 Mhz reference clocks (66 MHz corresponds to a 16 nanosecond clock period). If the buffer delay is not compenstated, then all of the circuits connected to the clock buffer operate 5 seconds out of phase with the referece clock. A fixed delay of 11 nanoseconds can be added onto the clock signal that the local circuits receive, so that they are in precise phase with the reference clock. The problem is that the 5 nanosecond delay of the clock buffer changes as the buffer heats up or cools down, or if the buffer's operating voltage fluctuates. An adaptive delay is required that delays the clock by as much or little time as required to keep the circuit in phase with the reference clock.
One well known circuit that compensates for variable propagation delays is the delay locked loop (DLL). FIG. 1 shows a conventional DLL circuit. The reference clock 17 is input to both the phase comparator 11 and to the delay line 10. The outputs of the delay line, called taps 14, are input to a multiplexer 13. In modern computer systems, consecutive taps produce outputs which are duplicates of the reference clock, but delayed by multiples of 60 picoseconds or less. FIG. 2 shows outputs of tap numbers zero (t0) and one (t1) along side the reference clock (CLK REF). Referring back to FIG. 1, the counter 12 selects which tap output 14 is propogated to the output 15 of the multiplexer 13. The output 15 of the multiplexer 13 is fed back to the other input 16 of the phase comparator 11, which outputs an indication of the phase error to the counter 12. The counter 12 responds to this phase error, counting upwards when CLK OUT 15 transitions before (leads) CLK REF 17, or counting downward when CLK OUT 15 transitions after (lags) CLK REF 17. The timing of the output 15 of the multiplexer 13 is advanced or delayed until its phase is coincident with the phase of the reference clock 17.
One problem with this circuit is that the delay line 10 can span several clock cycles. The number of clock cycles incorporated within the delay line is a function of the length of the delay line and the frequency of the input clock. Higher frequency clocks produce more cycles within a delay line of fixed length. Lower frequency clocks change more slowly over time and thus produce fewer cycles. The delay line must be long enough to hold one cycle of the slowest clock frequency used with it. If the computer operates at both 33 MHz and 66 MHz, then the delay line must be long enough to accommodate one 33 Mhz clock cycle. This same length will accommodate two 66 Mhz clock cycles. Thus when operating at 66 Mhz, the delay line contains two clock cycles.
Other factors besides frequency affect the number of clock cycles in the delay line. These include the operating temperature and operating voltage of the circuit. In modern computer circuits these factors often combine to produce a 4 to 1 ratio between the maximum and minimum number of clock cycles that appear in the delay line. The delay line will contain 4 times more clock cycles at the maximum combination of operating factors than at the minimum combination of factors. The most cycles will occur at the combination of highest clock frequency, lowest temperature, and highest operating voltage.
Multiple clock cycles within the delay line may cause the DLL to lock onto a tap which is less than ideal. The counter begins counting within the clock cycle it initializes into at power-up of the circuit. This clock cycle may not contain the tap which is optimum for locking the phase because of a phenomenon called jitter. As FIG. 3 shows, clock signals 60, 62, 64 output by taps on the delay line tend to jitter (vary) in time. The rising edge of an output does not always follow the rising edge of the input signal by a fixed delay. Instead, the delay varies by an error amount (jitter) which is proportional to a tap's depth within the delay line. Higher numbered taps located further from the delay line produce outputs with more jitter than lower numbered taps. This is a physical characteristic of delay lines, caused by noise and other environmental factors. It is not a characteristic of the reference clock, which tends to show very low jitter.
Therefore, a tap outputs more jitter than necessary if it is not within the first clock cycle contained by the delay line. The optimum tap is the one which minimizes the phase error and is also located within the first clock cycle within the delay line.
On power-up, the counter outputs a random value. It then proceeds to count up or down based upon the phase error corresponding to this random value. A reset signal can be applied to start the counter from 0, from which point it counts up to the first tap which minimizes the phase error. This is the optimum tap with the least jitter because it is within the first clock cycle within the delay line.
However, a system may contain circuits which must be operating during or immediately after the reset. Such circuits are especially common in modern high-speed computer systems. In these systems there is no time to ensure that the counter starts its count from 0 after reset. The delay involved may cause system failures or timing errors.
One solution is to produce two reset signals. One signal resets the counter a few tens of microseconds prior to the second signal which resets the system. This gives the counter time to count up to the first tap that locks the phase before the system reset is cleared. Systems without two resets cannot use this approach.
The present invention is an improved method and apparatus for selecting a range of taps for the counter to count over in a locked loop. The invention minimizes jitter in the output clock signal and does not require a separate reset signal to initialize the counter. The invention works irrespective of whether the phase of the output clock is leading or lagging the reference clock at power-on.